The present invention is directed to multi-processor systems and, more particularly, to testing the coherency of data stored in a memory shared by the processor cores through core interconnects.
In multi-processor systems with shared memory, two or more processing cores operate at the same time and can access simultaneously common memory locations. Precautions are taken so that when one of the processor cores has updated data at a common location, the other cores will not work on stale (out-of-date) data. The need for coherency exists whether the data is an operand or an instruction.
Multi-processor systems typically include caches, in which case precautions are taken that data copied into the caches remains coherent with the data in the corresponding main memory location and derived data in other locations. The precautions typically include enabling each processor core to have information whether the data in a particular memory location is the most recent updated data and various parameters are included in the caching structures to indicate the various potential states of cached data.
The complexity of the interactions between the different processor cores and the shared memory, caches and interconnects requires verification by testing the hardware design for multi-core cache-memory coherency scenarios under stress. Automatic test equipment (ATE) including a test pattern generator can apply test patterns of instructions to physical devices in order to identify causes of lack of data integrity. However, defective operations (bugs) are sufficiently few and far between for test run times to be excessively long before such bugs occur. Thus, there is a need for a test method that stresses shared memory and interconnects with the caches and processor cores by producing frequent and rapid transitions of state in the memory components, and heavy traffic and contention on the interconnects, in order for the bugs to appear with shorter test runs.